W83877ATF Datasheet, PDF (147/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
Bit 4 - bit 2: Reserved, fixed at 0.
SMI_EN (Bit 2): SMI output pin enable.
While an SMI event is raised on the output of the SMI logic, this bit determines whether the SMI
interrupt is generated on the SMI output SMI pin and on the Serial IRQ IRQSER pin while in Serial
IRQ mode.
0
disable
1
enable
Bit 1:Reserved.
UPULLEN (Bit 0): Enable the pull up of IRQSER pin in Serial IRQ mode.
0
disable the pull up of IRQSER pin.
1
enable the pull up of IRQSER pin.
8.2.49 Configuration Register 3B (CR3B), default=00H
Reserved for testing. Should be kept all 0's.
8.2.50 Configuration Register 40 (CR40), default=00H
When the device is in Extended Function mode and EFIR is 40H, the CR40 register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
URBIDLSTS
URAIDLSTS
FDCIDLSTS
PRTIDLSTS
reserved
reserved
reserved
reserved
Bit 7 - bit 4 : Reserved, fixed at 0.
Bit 3 - bit 0 : Devices' idle status.
These bits indicate that the individual device's idle timer expires due to no I/O access, IRQ, and
external input to the device respectively. These 4 bits are controlled by the printer port, FDC, UART
A, and UART B power down machines individually. The bits are set/cleared by W83877ATF
automatically. Writing a 1 can also clear this bit, and writing a 0 has no effect.
PRTIDLSTS (Bit 3): printer port idle status.
0
printer port is now in the working state.
1
printer port is now in the sleeping state due to no printer port access, IRQ, DMA
acknowledge, and no transition on BUSY, ACK , PE, SLCT, and ERR pins.
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Publication Release Date: April 1998
Version 0.51