W83877ATF Datasheet, PDF (105/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
Table 7-1 IRQSER Sampling periods
IRQ/Data Frame
Signal Sampled
1
IRQ0
2
IRQ1
3
SMI
4
IRQ3
5
IRQ4
6
IRQ5
7
IRQ6
8
IRQ7
9
IRQ8
10
IRQ9
11
IRQ10
12
IRQ11
13
IRQ12
14
IRQ13
15
IRQ14
16
IRQ15
17
IOCHCK
18
INTA
19
INTB
20
21
32:22
INTC
INTD
Unassigned
# of clocks past Start
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
95
7.3 Stop Frame
After all IRQ/Data Frames have beencompleted, the host controller will terminate IRQSER by a Stop
frame. Only the host controller can initiate the Stop frame by driving IRQSER low for 2 or 3 clocks. If
the Stop Frame is low for 2 clocks, the next IRQSER cycle's Sample mode is the Quiet mode. If the
Stop Frame is low for 3 clocks, the next IRQSER cycle's Sample mode is the Continuous mode.
7.4 Reset and Initialization
After MR reset, IRQSER Slaves are put into the Continuous(Idle) mode. The Host Controller is
responsibe for starting the initial IRQSER Cycle to collect system's IRQ/Data default values. The
system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for
subsequent IRQSER cycles. It's the Host Controller's responsibility to provide the default values to
8259's and other system logic before the first IRQSER cycle is performed. For IRQSER system
suspend, insertion, or removal application, the Host controller should be programmed into
Continuous(Idle) mode first. This is to guarantee IRQSER bus in the Idle state before the system
configuration changes.
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Publication Release Date: April 1998
Version 0.51