W83877ATF Datasheet, PDF (111/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
8.2.6 Configuration Register 5 (CR5), default = 00H
When the device is in Extended Function mode and EFIR is 05H, the CR5 register can be accessed
through EFDR. The bit definitions are as follows:
7 6 54 3 2 1
0
ECPFTHR0
ECPFTHR1
ECPFTHR2
ECPFTHR3
reserved
reserved
reserved
reserved
Bit 7- bit 4: Reserved
ECPFTHR3-0 (bit 3-0): These four bits define the FIFO threshold for the ECP mode parallel port. The
default value is 0000 after power-up.
8.2.7 Configuration Register 6 (CR6), default = 00H
When the device is in Extended Function mode and EFIR is 06H, the CR6 register can be accessed
through EFDR. The bit definitions are as follows:
7 65 4 3 21 0
reserved
FDCTRI
reserved
FDCPWD
FIPURDWM
SEL4FDD
reserved
reserved
Bit 7- bit 6: Reserved
SEL4FDD (Bit 5): Selects four FDD mode
0
Selects two FDD mode (default, see Table 8-2)
1
Selects four FDD mode
DSA , DSB , MOA and MOB output pins are encoded as show in Table 8-3 to select
four drives.
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Publication Release Date: April 1998
Version 0.51