W83877ATF Datasheet, PDF (149/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
PRTTRAPSTS (Bit 3): printer port trap status.
0
the printer port is now in the sleeping state.
1
the printer port is now in the working state due to any printer port access, any
IRQ, any DMA acknowledge, and any transition on BUSY, ACK , PE, SLCT, and
ERR pins.
FDCTRAPSTS (Bit 2): FDC trap status.
0
FDC is now in the sleeping state.
1
FDC is now in the working state due to any FDC access, any IRQ, any DMA
acknowledge, and any enabling of the motor enable bits in the DOR register.
URATRAPSTS (Bit 1): UART A trap status.
0
UART A is now in the sleeping state.
1
UART A is now in the working state due to any UART A access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins
transmitting a start bit, and any transition on MODEM control input lines.
URBTRAPSTS (Bit 0): UART B trap status.
0
UART B is now in the sleeping state.
1
UART B is now in the working state due to any UART B access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins
transmitting a start bit, and any transition on MODEM control input lines.
8.2.52 Configuration Register 42 (CR42), default=N/A
When the device is in Extended Function mode and EFIR is 42H, the CR42 register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
URBIRQSTS
URAIRQSTS
FDCIRQSTS
PRTIRQSTS
reserved
reserved
reserved
reserved
Bit 7 - bit 4 : Reserved, fixed at 0.
Bit 3 - bit 0 : Device's IRQ status .
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Publication Release Date: April 1998
Version 0.51