W83877ATF Datasheet, PDF (117/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
Bit 7: Reserved.
TXW4C (Bit 6):
This bit is active high. When active, the IR controller will wait for a 4-character period of time from the
end of last receiving before it can start transmitting data.
RXW4C (Bit 5):
This bit is active high. When active, the IR controller will wait for a 4-character period of time from the
end of last transmitting before it can start receiving data.
ENIFCHG (Bit 4):
This bit is active high. When active, it enables host interface mode change, which is determined by
IDENT (Bit 3) and MFM (Bit 2).
IDENT (Bit 3):
This bit indicates the type of drive being accessed and changes the level on RWC (pin 87).
0
RWC will be active low for high data rates (typically used for 3.5" drives)
1
RWC will be active high for high data rates (typically used for 5.25" drives)
When hardware reset or ENIFCHG is a logic 1, IDENT and MFM select one of three interface modes,
as shown in Table 8-5.
Table 8-5
IDENT
0
0
1
1
MFM
0
1
0
1
INTERFACE
Model 30 mode
PS/2 mode
AT mode
AT mode
MFM (Bit 2):
This bit and IDENT select one of the three interface modes (PS/2 mode, Model 30, or PC/AT mode).
INTVERTZ (Bit 1):
This bit determines the polarity of all FDD interface signals.
0
FDD interface signals are active low
1
FDD interface signals are active high
DRV2EN (Bit 0): PS/2 mode only
When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A.
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Publication Release Date: April 1998
Version 0.51