W83877ATF Datasheet, PDF (135/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
8.2.33 Configuration Register 29 (CR29)
When the device is in Extended Function mode and EFIR is 29, the CR29 register can be accessed
through EFDR. Default = 62H if CR6 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are
as follows:
765
43
21
0
IQNIQS0
IQNIQS1
IQNIQS2
IQNIQS3
FDCIQS0
FDCIQS1
FDCIQS2
FDCIQS3
FDCIQS3-FDCIQS0 (Bit 7-bit 4): Allocate interrupt resource for FDC.
IQNIQS3-IQNIQS0 (Bit 3-bit 0): Allocate interrupt resource for IRQIN.
8.2.34 Configuration Registers (CR2A)
When the device is in Extended Function mode and EFIR is 2AH, the CR2A register can be accessed
through EFDR. This register default value is 00₁₆. The bit definitions are as follows:
765
43
21
0
IRRXDRQSL0
IRRXDRQSL1
IRRXDRQSL2
IRRXDRQSL3
IRTXDRQSL0
IRTXDRQSL1
IRTXDRQSL2
IRTXDRQSL3
IRTXDRQSL (bit 7-bit 4): Transmitter DMA channel A through D selection when high speed infrared
(FIR/MIR) is used and enable DMA channel. Note that these bits is used in two DMA channels.
IRRXDRQSL(bit 3-bit 0): Receiver or Transmitter DMA channel A through selection when high speed
infrared (FIR/MIR) is used and enable DMA channel. Note that these bits act as RX DMA channel
selection if two DMA channel is used, or act as RX/TX DMA channel selection if single DMA channel
is used.
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Publication Release Date: April 1998
Version 0.51