W83877ATF Datasheet, PDF (57/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
Bit 1:
Bit 0:
Not used.
TXEMP_I - Transmitter Empty.
Set to 1 when transmitter (or, say, FIFO + Transmitter) is empty. Clear to 0 when this
register is read.
RXTH_I - Receiver Threshold Interrupt.
Set to 1 when (1) the Receiver Buffer Register (RBR) is equal to or larger than the
threshold level, (2) RBR occurs time-out if the receiver buffer register has valid data and
below the threshold level. Clear to 0 when RBR is less than threshold level from reading
RBR.
(2) UART FIFO Control Register (UFR):
Mode
Bit 7
Bit 6
Bit 5
Legacy RXFTL1 RXFTL0
0
UART (MSB) (LSB)
Advanced RXFTL1
UART (MSB)
Reset Value
0
RXFTL0
(LSB)
0
TXFTL1
(MSB)
0
Bit 4
0
TXFTL0
(LSB)
0
Bit 3
Bit 2
Bit 1
Bit 0
0 TXF_RST RXF_RST EN_FIFO
0 TXF_RST RXF_RST EN_FIFO
0
0
0
0
Legacy UART: The definition of this register is same as Legacy UART mode.
Advanced UART:
Bit 7, 6: RXFTL1, 0 - Receiver FIFO Threshold Level
Definition is same as Legacy UART, that is to determine the RXTH_I to become 1 when
the Receiver FIFO Threshold Level is equal or larger than the defined value shownbelow.
RXFTL1, 0
(Bit 7, 6)
00
01
10
11
RX FIFO Threshold Level RX FIFO Threshold Level
(FIFO Size: 16-byte)
(FIFO Size: 32-byte)
1
1
4
4
8
16
14
26
Note that the FIFO Size is referred to SET2.Reg4.
Bit 5, 4:
TXFTL1, 0 - Transmitter FIFO Threshold Level
To determine the TXTH_I (Transmitter Threshold Level Interrupt) is set to 1 when the
Transmitter Threshold Level is less than the programmed value shown as follows.
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Publication Release Date: April 1998
Version 0.51