W83877ATF Datasheet, PDF (103/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
7.0 SERIAL IRQ
W83877ATF supports a serial IRQ scheme. This allows a signal line to be used to report the legacy
ISA interrupt requests. Because more than one device may need to share the signal serial IRQ signal
line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is
transfered on the IRQSER signal, one cycle consisting of three frames types: a start frame, several
IRQ/Data frame, and one Stop frame. The serial interrupt scheme adheres to the Serial IRQ
Specification for PCI System, Version 6.0.
Timing Diagrams For IRQSER Cycle
Start Frame timing with source sampled a low pulse on IRQ1
PCICLK
IRQSER
SL
START FRAME
IRQ0 FRAME
IRQ1 FRAME
IRQ2 FRAME
or
H
H
R
T
S
R
T
S
R
T
S
R
T
1
START
Drive Source
IRQ1
Host Controller
H=Host Control
SL=Slave Control
1. Start Frame pulse can be 4-8 clocks wide.
None
R=Recovery
IRQ1
T=Turn-around
None
S=Sample
Stop Frame Timing with Host using 17 IRQSER sampling period
PCICLK
IRQSER
IRQ14
IRQ15
IOCHCK
FRAME
FRAME
FRAME
STOP FRAME
2
S
R
T
S
R
T
SR
T
I
H
R
T
STOP1
NEXT CYCLE
START3
Drive
None
H=Host Control
IRQ15
R=Recovery
None
T=Turn-around
Host Controller
S=Sample
I=Idle
1. Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
2. There may be none, one or more Idle states during the Stop Frame.
3. The next IRQSER cycle's Start Frame pulse may or may not start immediately after the turn-around clock of the Stip Frame.
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Publication Release Date: April 1998
Version 0.51