W83877ATF Datasheet, PDF (63/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
4.3.3 Set1 - Legacy Baud Rate Divisor Register
Address Register Name
Offset
Register Description
0
BLL
Baud Rate Divisor Latch (Low Byte)
1
BHL
Baud Rate Divisor Latch (High Byte)
2
ISR/UFR Interrupt Status or UART FIFO Control Register
3
UCR/SSR UART Control or Sets Select Register
4
HCR
Handshake Control Register
5
USR
UART Status Register
6
HSR
Handshake Status Register
7
UDR/ESCR User Defined Register
4.3.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)
The two registers of BLL and BHL are baud rate divisor latch in the legacy UART/SIR/ASK-IR mode.
Read/Write these registers, if set in Advanced UART mode, will occur backward operation, that is, will
go to legacy UART mode and clear some register values shown in the table below.
Set & Register
Set 0.Reg 4
Set 2.Reg 2
Set 4.Reg 3
Advanced Mode
DIS_BACK=×
Bit 7~5
Bit 0, 5, 7
Bit 2, 3
Legacy Mode
DIS_BACK=0
-
Bit 5, 7
-
Note that DIS_BACK=1 (Disable Backward operation) in legacy UART/SIR/ASK-IR mode will not
affect any register which can operate legacy SIR/ASK-IR.
4.3.3.2 Set1.Reg 2~7
These registers are defined the same as the Set 0 registers.
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Publication Release Date: April 1998
Version 0.51