W83877ATF Datasheet, PDF (70/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
These are 13-bit registers. A write to these registers will cause the transmitter frame length of a
package be programmed. These registers are only used in APM=1 (automatic package mode,
Set5.Reg4.bit5). When APM=1, the physical layer will split data stream to a programmed frame
length if the transmitted data is larger than the programmed frame length. When these registers are
read, they will return the number of bytes which have not been transmitted from a frame length
programmed.
4.3.6.5 Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
RFRLL
Reset Value
RFRLH
Reset Value
bit 7
0
-
-
bit 6
0
-
-
bit 5
bit 4
bit 3
0
0
0
-
bit 12 bit 11
-
0
0
Bit 2
bit 2
0
bit 10
0
Bit 1
bit 1
0
bit 9
0
Bit 0
bit 0
0
bit 8
0
These are 13-bit registers which combine to form a 13-bit up counter. By programming these
registers, the receiver frame length will be limited to the programmed frame length. If the received
frame length is larger than the programmed receiver frame length, the bit of MX_LEX (Maximum
Length Exceed) will be set to 1. Simultaneously, the receiver will not receive any data to RX FIFO
until the next start flag in the next frame, which is defined in the physical layer IrDA 1.1, is reached;
the received data then begins to write to RX FIFO. Reading these registers will return the number of
received data bytes from the receiver for a frame.
4.3.7 Set 5 - Flow control and IR control and Frame Status FIFO registers
Address Register Name
Offset
Register Description
0
FCBLL Flow Control Baud Rate Divisor Latch Register (Low Byte)
1
FCBHL Flow Control Baud Rate Divisor Latch Register (High Byte)
2
FC_MD Flow Control Mode Operation
3
SSR
Sets Select Register
4
IRCFG1 Infrared Config Register
5
FS_FO Frame Status FIFO Register
6
RFRLFL Receiver Frame Length FIFO Low Byte
7
RFRLFH Receiver Frame Length FIFO High Byte
4.3.7.1 Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL)
If flow control occurs from MIR/FIR mode change to SIR mode, then the pre-programming baud rate
of FCBLL/FCBHL is loaded to advanced baud rate divisor latch (ADBLL/ADBHL).
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Publication Release Date: April 1998
Version 0.51