W83877ATF Datasheet, PDF (156/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
by the BIOS software and BM_RLD is set by the ACPI software, an SCI interrupt is raised. Writing a
1 to BM_CNTRL sets it to logic 1 and also sets BM_STS to logic 1; Writing a 0 to BM_CNTRL has no
effect. Writing a 1 to BM_STS clears it to logic 0 and also clears BM_CNTRL to logic 0; writing a 0 to
BM_STS has no effect.
8.3.2 Power Management Timer
In the ACPI specification, a power management timer is required. The power management timer is a
24-bit fixed rate free running count-up timer that runs off a 3.579545MHZ clock. The power
management timer has the corresponding status bit (TMR_STS) and enable bit (TMR_EN). The
TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1 or from 1 to 0. If the
TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. Three registers are
used to read the timer value; they are located in the PM1 register block. The power management
timer has one enable bit (TMR_ON) to turn if on or off. The TMR_ON is located in GPE register
block. If it is cleared to 0, the power management timer function will not work. There are no timer
reset requirements, except that the timer should function after power-up. See the following figure for
an illustration.
TMR_ON
3.579545 MHz
24 bit
counter
Bits (23-0)
24
TMR_VAL
TMR_STS
TMR_EN
To SCI Logic
8.4 ACPI Registers (ACPIRs)
The ACPI register model consists of the fixed register blocks that perform the ACPI functuions. A
register block may be a event register block which deals with ACPI events, or a control register block
which deals with control features. The ordering in the event register block is the status register,
followed by the enable register.
Each event register, if implemented, contains two egisters: a status register and an enable register,
both in 16-bit size. The status register indicates what defined function needs the ACPI System Control
Interrupt (SCI). When the hardware event occurs, the defined status bit is set. However, to generate
the SCI, the associated enable bit must be set. If the enable bit is not set, the software can examine
the state of the hardware event by reading the status bit without generating an SCI interrupt.
Any status bit, unless otherwise noted, can only be set by some defined hardware event. It is cleared
by writing a 1 to its bit position; writing a 0 has no effect. Except forsome special status bits, every
status bit has an assiciated enable bit in the same bit position in the enable register. Those status bits
which have no respective enable bit are read for special purposes. Reserved or un-implemented
enable bits always return zero, and writing to these bits should have no effect.
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Publication Release Date: April 1998
Version 0.51