W83877ATF Datasheet, PDF (71/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
4.3.7.2 Set5.Reg2 - Flow Control mode Operation (FC_MD)
These registers control flow control mode operation as shown in the table below.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FC_MD FC_MD2 FC_MD1 FC_MD0
-
FC_DSW EN_FD EN_BRFC EN_FC
Reset Value
0
0
0
0
0
0
0
0
Bit 7~5
Bit 4:
Bit 3:
FC_MD2 - Flow Control mode
When flow control state occurs, these bits will be loaded to AD_MD2~0 of advanced HSR
(Handshake Status Register). These three bits are defined the same as AD_MD2~0.
Reserved, write 0.
FC_DSW - Flow Control DMA Channel Swap
Write to 1, when flow control state occurs enables DMA channel of both transmitter and
receiver to be swapped.
Bit 2:
Bit 1:
Bit 0:
FC_DSW
Next Mode After Flow Control Occurred
0
Receiver Channel
1
Transmitter Channel
EN_FD - Enable Flow DMA Control
Write to 1 enables use of DMA channel when flow control has occurred.
EN_BRFC - Enable Baud Rate Flow Control
Write to 1 enables FC_BLL/FC_BHL (Flow Control Baud Rate Divider Latch, in
Set5.Reg1~0) to be loaded to advanced baud rate divisor latch (ADBLL/ADBHL, in
Set2.Reg1~0).
EN_FC - Enable Flow Control
Write to 1 allows use of flow control function and activation of bit 7~1 of this register.
4.3.7.3 Set5.Reg3 - Sets Select Register (SSR)
A write to this register will change Set of register. Reading this register will return EC₁₆.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SSR
default Value
SSR7
1
SSR6
1
SSR5
1
SSR4
0
SSR3
1
SSR2
1
SRR1
0
Bit 0
SRR0
0
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Publication Release Date: April 1998
Version 0.51