W83877ATF Datasheet, PDF (58/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
TXFTL1, 0
(Bit 5, 4)
00
01
10
11
TX FIFO Threshold Level
(FIFO Size: 16-byte)
1
3
9
13
TX FIFO Threshold Level
(FIFO Size: 32-byte)
1
7
17
25
Bit 3 ~0 Same Legacy UART mode
4.3.2.4 Set0.Reg3 - UART Control Register/Set Select Register (UCR/SSR):
These two registers share the same address. In any Set, Set Select Register (SSR) can be
programmed to desired Set, but UART Control Register can be programmed only in Set 0 and Set 1,
that is, in other Sets programming this register will have no effect. The mapping of entry Set and
programming value is shown as follows.
SSR Bits
76543210
0×× ×××××
1 ^{Any value but not used in SET 2~7}
11100000
11100100
11101000
11111100
11110000
11110100
Hex Value
¡Ð
¡Ð
0xE0
0xE4
0xE8
0xEC
0xF0
0xF4
Selected
Set
Set 0
Set1
Set 2
Set 3
Set 4
Set 5
Set 6
Set 7
UART Control Register: Defined legacy UART.
4.3.2.5 Set0.Reg4 - Handshake Control Register (HCR)
Mode
B7
B6
B5
B4
B3
B2
0
0
0
XLOOP EN_IRQ LP_RI
Legacy
UART
Advanced AD_MD2 AD_MD1 AD_MD0 SIR_PLS
UART
Reset Value
0
0
0
0
TX_WT
0
EN_DMA
0
B1
RTS
RTS
0
B0
DTR
DTR
0
- 54 -
Publication Release Date: April 1998
Version 0.51