W83877ATF Datasheet, PDF (140/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
EN24MX2:
0
Using internal circuit type one to generate 48M Hz when CLKIN is 24M Hz. (Default)
1
Using internal circuit type two to generate 48M Hz when CLKIN is 24M Hz.
DIS_BST(Bit3): Disable FDC DMA Burst Mode.
0
Enable FDC burst mode. (Default)
1
Disable FDC burst mode.
8.2.39 Configuration Register 31 (CR31), default=00H
When the device is in Extended Function mode and EFIR is 31H, the CR31 register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
reserved
reserved
IRQMODS
reserved
SCIIRQ0
SCIIRQ1
SCIIRQ2
SCIIRQ3
SCIIRQ3 ~ SCIIRQ0 (Bit 7 - bit 4):
The four bits select one IRQ pin for the SCI signal except for dedicated SCI signal output pin. Any
unselected pin is in tri-state.
CR31[7:4]
0000
0001
0010
0011
0100
0101
0110
0111
1000
None (default)
IRQ_A
IRQ_B
IRQ_C
IRQ_D
IRQ_E
IRQ_F
IRQ_G
IRQ_H
Mapped IRQ pin
While in the Serial IRQ mode (IRQMODS=1, CR31 bit 2), the above selection is invalid and all the
IRQ signal pins, from IRQ_A to IRQ_H, are all in tri-state. The SCI interrupt output is dedicated to the
SERIRQ pin. For the host controller to correctly sample the SCI interrupt, the SCI interrupt should be
programmed to appear in one of IRQ/Data Frame sampling periods.
In Serial IRQ mode, the definition of SCIIQS3-SCIIQS0 (bit 7-bit 4) is as follows:
SCIIQS3-SCIIQS0 (bit 7-bit 4): Select the IRQ/Data sampling period on the SERIRQ pin.
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Publication Release Date: April 1998
Version 0.51