W83877ATF Datasheet, PDF (73/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
FSFDR - Frame Status FIFO Data Ready
Indicates that there is valid data in frame status FIFO bottom.
LST_FR - Lost Frame
Set to 1 when one or more than one frame has been lost.
Reserved.
MX_LEX - Maximum Frame Length Exceed
Set to 1 when programmed maximum frame length defined Set4.Reg6 and Set4.Reg7 are
exceeded. This bit is frame status FIFO bottom. Reading this bit will return a valid value
when FSFDR=1 (Frame Status FIFO Data Ready).
PHY_ERR - Physical Error
During receiving data, any physical layer error, defined IrDA 1.1, will be set to 1 in this bit.
This bit is frame status FIFO bottom. Reading this bit will return a valid value when
FSFDR=1 (Frame Status FIFO Data Ready).
CRC_ERR - CRC Error
Set to 1 when a bad CRC is received in a frame. This CRC belongs to physical layer
defined in IrDA 1.1. This bit is frame status FIFO bottom. Reading this bit will return a valid
value when FSFDR=1 (Frame Status FIFO Data Ready).
RX_OV - Received Data Overrun
Set to 1 when Received data in FIFO overrun occurs.
FSF_OV - Frame Status FIFO Overrun
Set to 1 When frame status FIFO overrun occurs.
4.3.7.5 Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame Number
(LST_NU)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RFLFL/
LST_NU
Reset Value
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
RFLFH
-
-
-
Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Reset Value
0
0
0
0
0
0
0
0
Receiver Frame Length FIFO (RFLFL/RFLFH):
These registers are 13-bit. Reading these registers will return received frame length. When read the
register of RFLFH will pop-up another frame status and frame length if FSFDR=1 (Set5.Reg4.Bit7).
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Publication Release Date: April 1998
Version 0.51