LM3S5G51 Datasheet, PDF (96/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

The Cortex-M3 Processor
2.5.3
2.5.4
Table 2-9. Interrupts (continued)
Vector Number
45
46
47
48
49
50
51
52
53
54
55
56
57-58
59
60
61
62
63
64
65
66
67
68
69
70
Interrupt Number (Bit
in Interrupt Registers)
29
30
31
32
33
34
35
36
37
38
39
40
41-42
43
44
45
46
47
48
49
50
51
52
53
54
Vector Address or
Offset
0x0000.00B4
0x0000.00B8
0x0000.00BC
0x0000.00C0
0x0000.00C4
0x0000.00C8
0x0000.00CC
0x0000.00D0
0x0000.00D4
0x0000.00D8
0x0000.00DC
0x0000.00E0
-
0x0000.00EC
0x0000.00F0
-
0x0000.00F8
0x0000.00FC
0x0000.0100
0x0000.0104
0x0000.0108
0x0000.010C
0x0000.0110
-
0x0000.0118
Description
Flash Memory Control
GPIO Port F
GPIO Port G
GPIO Port H
UART2
SSI1
Timer 3A
Timer 3B
I²C1
QEI1
CAN0
CAN1
Reserved
Hibernation Module
USB
Reserved
µDMA Software
µDMA Error
ADC1 Sequence 0
ADC1 Sequence 1
ADC1 Sequence 2
ADC1 Sequence 3
I²S0
Reserved
GPIO Port J
Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 94. Figure 2-6 on page 97 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
96
January 23, 2012
Texas Instruments-Production Data