LM3S5G51 Datasheet, PDF (436/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

General-Purpose Input/Outputs (GPIOs)
Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 437).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be set. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from
the address used to access the data register, bits [9:2]. Bits that are set in the address mask cause
the corresponding bits in GPIODATA to be read, and bits that are clear in the address mask cause
the corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
GPIO Data (GPIODATA)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DATA
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7:0
Name
reserved
DATA
Type
RO
R/W
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00
GPIO Data
This register is virtually mapped to 256 locations in the address space.
To facilitate the reading and writing of data to these registers by
independent drivers, the data read from and written to the registers are
masked by the eight address lines [9:2]. Reads from this register return
its current state. Writes to this register only affect bits that are not masked
by ADDR[9:2] and are configured as outputs. See “Data Register
Operation” on page 429 for examples of reads and writes.
436
January 23, 2012
Texas Instruments-Production Data