LM3S5G51 Datasheet, PDF (483/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Stellaris^® LM3S5G51 Microcontroller
(GPTMTBMR) register (see page 498). When in one of the concatentated modes, Timer A and Timer
B can only operate in one mode. However, when configured in an individual mode, Timer A and
Timer B can be independently configured in any combination of the individual modes.
10.3.1
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters Timer A and Timer B are initialized to all
1s, along with their corresponding load registers: the GPTM Timer A Interval Load (GPTMTAILR)
register (see page 513) and the GPTM Timer B Interval Load (GPTMTBILR) register (see page 514)
and shadow registers: the GPTM Timer A Value (GPTMTAV) register (see page 523) and the GPTM
Timer B Value (GPTMTBV) register (see page 524). The prescale counters are initialized to 0x00:
the GPTM Timer A Prescale (GPTMTAPR) register (see page 517) and the GPTM Timer B Prescale
(GPTMTBPR) register (see page 518).
10.3.2
Timer Modes
This section describes the operation of the various timer modes. When using Timer A and Timer B
in concatenated mode, only the Timer A control and status bits must be used; there is no need to
use Timer B control and status bits. The GPTM is placed into individual/split mode by writing a value
of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 495). In the following sections,
the variable "n" is used in bit field and register names to imply either a Timer A function or a Timer
B function. Throughout this section, the timeout event in down-count mode is 0x0 and in up-count
mode is the value in the GPTM Timer n Interval Load (GPTMTnILR) and the optional GPTM Timer
n Prescale (GPTMTnPR) registers.
10.3.2.1
One-Shot/Periodic Timer Mode
The selection of one-shot or periodic mode is determined by the value written to the TnMR field of
the GPTM Timer n Mode (GPTMTnMR) register (see page 496). The timer is configured to count
up or down using the TnCDIR bit in the GPTMTnMR register.
When software sets the TnEN bit in the GPTM Control (GPTMCTL) register (see page 500), the
timer begins counting up from 0x0 or down from its preloaded value. Alternatively, if the TnWOT bit
is set in the GPTMTnMR register, once the TnEN bit is set, the timer waits for a trigger to begin
counting (see the section called “Wait-for-Trigger Mode” on page 484). Table 10-5 on page 483 shows
the values that are loaded into the timer registers when the timer is enabled.
Table 10-5. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes
Register
TnR
TnV
Count Down Mode
GPTMTnILR
GPTMTnILR
Count Up Mode
0x0
0x0
When the timer is counting down and it reaches the timeout event (0x0), the timer reloads its start
value from the GPTMTnILR and the GPTMTnPR registers on the next cycle. When the timer is
counting up and it reaches the timeout event (the value in the GPTMTnILR and the optional
GPTMTnPR registers), the timer reloads with 0x0. If configured to be a one-shot timer, the timer
stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer,
the timer starts counting again on the next cycle.
In periodic, snap-shot mode (TnMR field is 0x2 and the TnSNAPS bit is set in the GPTMTnMR
register), the value of the timer at the time-out event is loaded into the GPTMTnR register. The
free-running counter value is shown in the GPTMTnV register. In this manner, software can determine
the time elapsed from the interrupt assertion to the ISR entry by examining the snapshot values
January 23, 2012
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