LM3S5G51 Datasheet, PDF (7/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Stellaris^® LM3S5G51 Microcontroller
12.3.3 Hardware Sample Averaging Circuit ............................................................................. 557
12.3.4 Analog-to-Digital Converter .......................................................................................... 558
12.3.5 Differential Sampling ................................................................................................... 562
12.3.6 Internal Temperature Sensor ........................................................................................ 564
12.3.7 Digital Comparator Unit ............................................................................................... 565
12.4 Initialization and Configuration ..................................................................................... 569
12.4.1 Module Initialization ..................................................................................................... 569
12.4.2 Sample Sequencer Configuration ................................................................................. 570
12.5 Register Map .............................................................................................................. 570
12.6 Register Descriptions .................................................................................................. 572
13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 631
13.1 Block Diagram ............................................................................................................ 632
13.2 Signal Description ....................................................................................................... 632
13.3 Functional Description ................................................................................................. 634
13.3.1 Transmit/Receive Logic ............................................................................................... 634
13.3.2 Baud-Rate Generation ................................................................................................. 635
13.3.3 Data Transmission ...................................................................................................... 636
13.3.4 Serial IR (SIR) ............................................................................................................. 636
13.3.5 ISO 7816 Support ....................................................................................................... 637
13.3.6 Modem Handshake Support ......................................................................................... 637
13.3.7 LIN Support ................................................................................................................ 639
13.3.8 FIFO Operation ........................................................................................................... 640
13.3.9 Interrupts .................................................................................................................... 641
13.3.10 Loopback Operation .................................................................................................... 642
13.3.11 DMA Operation ........................................................................................................... 642
13.4 Initialization and Configuration ..................................................................................... 642
13.5 Register Map .............................................................................................................. 643
13.6 Register Descriptions .................................................................................................. 645
14 Synchronous Serial Interface (SSI) .................................................................... 695
14.1 Block Diagram ............................................................................................................ 696
14.2 Signal Description ....................................................................................................... 696
14.3 Functional Description ................................................................................................. 697
14.3.1 Bit Rate Generation ..................................................................................................... 698
14.3.2 FIFO Operation ........................................................................................................... 698
14.3.3 Interrupts .................................................................................................................... 698
14.3.4 Frame Formats ........................................................................................................... 699
14.3.5 DMA Operation ........................................................................................................... 706
14.4 Initialization and Configuration ..................................................................................... 707
14.5 Register Map .............................................................................................................. 708
14.6 Register Descriptions .................................................................................................. 709
15 Inter-Integrated Circuit (I²C) Interface ................................................................ 737
15.1 Block Diagram ............................................................................................................ 738
15.2 Signal Description ....................................................................................................... 738
15.3 Functional Description ................................................................................................. 739
15.3.1 I²C Bus Functional Overview ........................................................................................ 739
15.3.2 Available Speed Modes ............................................................................................... 741
15.3.3 Interrupts .................................................................................................................... 742
15.3.4 Loopback Operation .................................................................................................... 743
January 23, 2012
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