LM3S5G51 Datasheet, PDF (1152/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Signal Tables
Table 23-7. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PD5
I/O
TTL
GPIO port D bit 5.
AIN6
I
Analog Analog-to-digital converter input 6.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
C6
CCP4
I/O
TTL
Capture/Compare/PWM 4.
I2S0RXMCLK
I/O
TTL
I²S module 0 receive master clock.
U2Rx
I
TTL
UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
VDDA
C7
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in Table 25-2 on page 1186, regardless of system
implementation.
PH1
I/O
TTL
GPIO port H bit 1.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
C8
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
PH0
I/O
TTL
GPIO port H bit 0.
CCP6
I/O
TTL
Capture/Compare/PWM 6.
C9
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
PG7
I/O
TTL
GPIO port G bit 7.
C10
CCP5
I/O
TTL
Capture/Compare/PWM 5.
PhB1
I
TTL
QEI module 1 phase B.
C11
USB0DM
I/O
Analog Bidirectional differential data pin (D- per USB specification) for
USB0.
C12
USB0DP
I/O
Analog Bidirectional differential data pin (D+ per USB specification) for
USB0.
D1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
VDDC
D3
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 25-6 on page 1191.
PH3
I/O
TTL
GPIO port H bit 3.
Fault0
D10
PhB0
I
TTL
PWM Fault 0.
I
TTL
QEI module 0 phase B.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
PH2
I/O
TTL
GPIO port H bit 2.
C1o
D11
Fault3
O
TTL
Analog comparator 1 output.
I
TTL
PWM Fault 3.
IDX1
I
TTL
QEI module 1 index.
1152
Texas Instruments-Production Data
January 23, 2012