LM3S5G51 Datasheet, PDF (11/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Stellaris^® LM3S5G51 Microcontroller
List of Figures
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Stellaris LM3S5G51 Microcontroller High-Level Block Diagram ............................... 44
CPU Block Diagram ............................................................................................. 66
TPIU Block Diagram ............................................................................................ 67
Cortex-M3 Register Set ........................................................................................ 69
Bit-Band Mapping ................................................................................................ 90
Data Storage ....................................................................................................... 91
Vector Table ........................................................................................................ 97
Exception Stack Frame ........................................................................................ 99
SRD Use Example ............................................................................................. 113
JTAG Module Block Diagram .............................................................................. 174
Test Access Port State Machine ......................................................................... 177
IDCODE Register Format ................................................................................... 183
BYPASS Register Format ................................................................................... 183
Boundary Scan Register Format ......................................................................... 184
Basic RST Configuration .................................................................................... 188
External Circuitry to Extend Power-On Reset ....................................................... 188
Reset Circuit Controlled by Switch ...................................................................... 189
Power Architecture ............................................................................................ 192
Main Clock Tree ................................................................................................ 195
Hibernation Module Block Diagram ..................................................................... 290
Using a Crystal as the Hibernation Clock Source ................................................. 293
Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 293
Internal Memory Block Diagram .......................................................................... 316
μDMA Block Diagram ......................................................................................... 363
Example of Ping-Pong μDMA Transaction ........................................................... 369
Memory Scatter-Gather, Setup and Configuration ................................................ 371
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 372
Peripheral Scatter-Gather, Setup and Configuration ............................................. 374
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 375
Digital I/O Pads ................................................................................................. 427
Analog/Digital I/O Pads ...................................................................................... 428
GPIODATA Write Example ................................................................................. 429
GPIODATA Read Example ................................................................................. 429
GPTM Module Block Diagram ............................................................................ 479
Timer Daisy Chain ............................................................................................. 485
Input Edge-Count Mode Example ....................................................................... 487
16-Bit Input Edge-Time Mode Example ............................................................... 488
16-Bit PWM Mode Example ................................................................................ 489
WDT Module Block Diagram .............................................................................. 526
Implementation of Two ADC Blocks .................................................................... 551
ADC Module Block Diagram ............................................................................... 552
ADC Sample Phases ......................................................................................... 556
Doubling the ADC Sample Rate .......................................................................... 557
Skewed Sampling .............................................................................................. 557
Sample Averaging Example ............................................................................... 558
January 23, 2012
11
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