LM3S5G51 Datasheet, PDF (26/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Table of Contents
Register 2:
Register 3:
Register 4:
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Register 7:
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Register 9:
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Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 755
I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 760
I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 761
I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 762
I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 763
I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 764
I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 765
I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 766
I²C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 767
I²C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 768
I²C Slave Data (I2CSDR), offset 0x808 ........................................................................... 770
I²C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 771
I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 772
I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 773
I²C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 774
Inter-Integrated Circuit Sound (I²S) Interface ............................................................................ 775
Register 1: I²S Transmit FIFO Data (I2STXFIFO), offset 0x000 .......................................................... 788
Register 2: I²S Transmit FIFO Configuration (I2STXFIFOCFG), offset 0x004 ...................................... 789
Register 3: I²S Transmit Module Configuration (I2STXCFG), offset 0x008 .......................................... 790
Register 4: I²S Transmit FIFO Limit (I2STXLIMIT), offset 0x00C ........................................................ 792
Register 5: I²S Transmit Interrupt Status and Mask (I2STXISM), offset 0x010 ..................................... 793
Register 6: I²S Transmit FIFO Level (I2STXLEV), offset 0x018 .......................................................... 794
Register 7: I²S Receive FIFO Data (I2SRXFIFO), offset 0x800 .......................................................... 795
Register 8: I²S Receive FIFO Configuration (I2SRXFIFOCFG), offset 0x804 ...................................... 796
Register 9: I²S Receive Module Configuration (I2SRXCFG), offset 0x808 ........................................... 797
Register 10: I²S Receive FIFO Limit (I2SRXLIMIT), offset 0x80C ......................................................... 800
Register 11: I²S Receive Interrupt Status and Mask (I2SRXISM), offset 0x810 ..................................... 801
Register 12: I²S Receive FIFO Level (I2SRXLEV), offset 0x818 ........................................................... 802
Register 13: I²S Module Configuration (I2SCFG), offset 0xC00 ............................................................ 803
Register 14: I²S Interrupt Mask (I2SIM), offset 0xC10 ......................................................................... 805
Register 15: I²S Raw Interrupt Status (I2SRIS), offset 0xC14 ............................................................... 807
Register 16: I²S Masked Interrupt Status (I2SMIS), offset 0xC18 ......................................................... 809
Register 17: I²S Interrupt Clear (I2SIC), offset 0xC1C ......................................................................... 811
Controller Area Network (CAN) Module ..................................................................................... 812
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 834
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 836
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 839
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 840
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 841
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 842
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 844
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 845
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 845
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 846
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 846
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 849
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January 23, 2012
Texas Instruments-Production Data