LM3S5G51 Datasheet, PDF (789/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Stellaris^® LM3S5G51 Microcontroller
Register 2: I²S Transmit FIFO Configuration (I2STXFIFOCFG), offset 0x004
This register configures the sample for dual-channel operation. In Stereo mode, the LRS bit toggles
between left and right samples as the Transmit FIFO is written. The left sample is written first,
followed by the right.
I2S Transmit FIFO Configuration (I2STXFIFOCFG)
Base 0x4005.4000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CSS
LRS
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:2
1
Name
reserved
CSS
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0
Compact Stereo Sample Size
Value Description
0 The transmitter is in Compact 16-bit Stereo Mode with a 16-bit
sample size.
1 The transmitter is in Compact 8-bit Stereo Mode with an 8-bit
sample size.
0
LRS
R/W
0
Left-Right Sample Indicator
Value Description
0 The left sample is the next position.
1 The right sample is the next position.
In Mono mode and Compact stereo mode, this bit toggles as if it were
in Stereo mode, but it has no meaning and should be ignored.
January 23, 2012
789
Texas Instruments-Production Data