LM3S5G51 Datasheet, PDF(1159/1266 Page) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

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LM3S5G51 Datasheet, PDF (1159/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

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StellarisÂ® LM3S5G51 Microcontroller

Table 23-7. Signals by Pin Number (continued)

Pin Number

Pin Name

Pin Type Buffer Typea Description

PA7

I/O

TTL

GPIO port A bit 7.

CAN0Tx

O

TTL

CAN module 0 transmit.

CCP3

I/O

TTL

Capture/Compare/PWM 3.

CCP4

I/O

TTL

Capture/Compare/PWM 4.

M6

I2C1SDA

I/O

OD

I2C module 1 data.

PWM1

O

TTL

PWM 1. This signal is controlled by PWM Generator 0.

PWM5

O

TTL

PWM 5. This signal is controlled by PWM Generator 2.

U1DCD

I

TTL

UART module 1 Data Carrier Detect modem status input signal.

USB0PFLT

I

TTL

Optionally used in Host mode by an external power source to

indicate an error state by that power source.

PG5

I/O

TTL

GPIO port G bit 5.

CCP5

I/O

TTL

Capture/Compare/PWM 5.

Fault1

I

TTL

PWM Fault 1.

M7

I2S0RXSCK

I/O

TTL

I2S module 0 receive clock.

IDX0

I

TTL

QEI module 0 index.

U1DTR

O

TTL

UART module 1 Data Terminal Ready modem status input signal.

PF6

I/O

TTL

GPIO port F bit 6.

CCP1

I/O

TTL

Capture/Compare/PWM 1.

M8

I2S0TXMCLK

I/O

TTL

I2S module 0 transmit master clock.

PhA0

I

TTL

QEI module 0 phase A.

U1RTS

O

TTL

UART module 1 Request to Send modem flow control output line.

PF0

I/O

TTL

GPIO port F bit 0.

CAN1Rx

I

TTL

CAN module 1 receive.

I2S0TXSD

I/O

TTL

I2S module 0 transmit data.

M9

PWM0

O

TTL

PWM 0. This signal is controlled by PWM Generator 0.

PhB0

I

TTL

QEI module 0 phase B.

U1DSR

I

TTL

UART module 1 Data Set Ready modem output control line.

M10

WAKE

I

TTL

An external input that brings the processor out of Hibernate mode

when asserted.

M11

OSC1

O

Analog Main oscillator crystal output. Leave unconnected when using a

single-ended clock source.

M12

HIB

O

OD

An output that indicates the processor is in Hibernate mode.

a. The TTL designation indicates the pin has TTL-compatible voltage levels.

Table 23-8. Signals by Signal Name

Pin Name

AIN0

AIN1

AIN2

AIN3

AIN4

Pin Number Pin Mux / Pin

Assignment

B1

PE7

A1

PE6

B3

PE5

B2

PE4

A2

PD7

Pin Type

I

I

I

I

I

Buffer Typea Description

Analog

Analog

Analog

Analog

Analog

Analog-to-digital converter input 0.

Analog-to-digital converter input 1.

Analog-to-digital converter input 2.

Analog-to-digital converter input 3.

Analog-to-digital converter input 4.

January 23, 2012

Texas Instruments-Production Data

1159

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