LM3S5G51 Datasheet, PDF (1153/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Stellaris^® LM3S5G51 Microcontroller
Table 23-7. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PB1
I/O
TTL
GPIO port B bit 1. This pin is not 5-V tolerant.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
PWM3
D12
U1Tx
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
USB0VBUS
I/O
Analog This signal is used during the session request protocol. This signal
allows the USB PHY to both sense the voltage level of VBUS, and
pull up VBUS momentarily during VBUS pulsing.
E1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
E2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
LDO
E3
-
Power Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. The LDO
pin must also be connected to the VDDC pins at the board level in
addition to the decoupling capacitor(s).
E10
VDD
-
Power Positive supply for I/O and some logic.
PB3
I/O
TTL
GPIO port B bit 3.
Fault0
I
TTL
PWM Fault 0.
E11
Fault3
I
TTL
PWM Fault 3.
I2C0SDA
I/O
OD
I²C module 0 data.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
PB0
I/O
TTL
GPIO port B bit 0. This pin is not 5-V tolerant.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
U1Rx
E12
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
USB0ID
I
Analog This signal senses the state of the USB ID signal. The USB PHY
enables an integrated pull-up, and an external element (USB
connector) indicates the initial state of the USB controller (pulled
down is the A side of the cable and pulled up is the B side).
F1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
F2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
PJ0
I/O
TTL
GPIO port J bit 0.
F3
I2C1SCL
I/O
OD
I²C module 1 clock.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PH5
I/O
TTL
GPIO port H bit 5.
F10
Fault2
I
TTL
PWM Fault 2.
SSI1Fss
I/O
TTL
SSI module 1 frame.
F11
GND
-
Power Ground reference for logic and I/O pins.
F12
GND
-
Power Ground reference for logic and I/O pins.
January 23, 2012
Texas Instruments-Production Data
1153