LM3S5G51 Datasheet, PDF (787/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Stellaris^® LM3S5G51 Microcontroller
Table 16-10. Inter-Integrated Circuit Sound (I²S) Interface Register Map
Offset Name
0x000 I2STXFIFO
0x004 I2STXFIFOCFG
0x008 I2STXCFG
0x00C I2STXLIMIT
0x010 I2STXISM
0x018 I2STXLEV
0x800 I2SRXFIFO
0x804 I2SRXFIFOCFG
0x808 I2SRXCFG
0x80C I2SRXLIMIT
0x810 I2SRXISM
0x818 I2SRXLEV
0xC00 I2SCFG
0xC10 I2SIM
0xC14 I2SRIS
0xC18 I2SMIS
0xC1C I2SIC
Type
WO
R/W
R/W
R/W
R/W
RO
RO
R/W
R/W
R/W
R/W
RO
R/W
R/W
RO
RO
WO
Reset
Description
0x0000.0000
0x0000.0000
0x1400.7DF0
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x1400.7DF0
0x0000.7FFF
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
I2S Transmit FIFO Data
I2S Transmit FIFO Configuration
I2S Transmit Module Configuration
I2S Transmit FIFO Limit
I2S Transmit Interrupt Status and Mask
I2S Transmit FIFO Level
I2S Receive FIFO Data
I2S Receive FIFO Configuration
I2S Receive Module Configuration
I2S Receive FIFO Limit
I2S Receive Interrupt Status and Mask
I2S Receive FIFO Level
I2S Module Configuration
I2S Interrupt Mask
I2S Raw Interrupt Status
I2S Masked Interrupt Status
I2S Interrupt Clear
See
page
788
789
790
792
793
794
795
796
797
800
801
802
803
805
807
809
811
16.6
Register Descriptions
The remainder of this section lists and describes the I²S registers, in numerical order by address
offset.
January 23, 2012
787
Texas Instruments-Production Data