LM3S5G51 Datasheet, PDF (19/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Stellaris^® LM3S5G51 Microcontroller
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Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 132
Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 132
Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 132
Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 132
Interrupt 52-54 Priority (PRI13), offset 0x434 ................................................................... 132
Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 134
Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 135
CPU ID Base (CPUID), offset 0xD00 ............................................................................... 137
Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 138
Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 141
Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 142
System Control (SYSCTRL), offset 0xD10 ....................................................................... 144
Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 146
System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 148
System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 149
System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 150
System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 151
Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 155
Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 161
Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 162
Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 163
MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 164
MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 165
MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 167
MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 168
MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 168
MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 168
MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 168
MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 170
MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 170
MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 170
MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 170
System Control ............................................................................................................................ 185
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 204
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 206
Register 3: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 207
Register 4: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 209
Register 5: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 211
Register 6: Reset Cause (RESC), offset 0x05C ................................................................................ 213
Register 7: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 215
Register 8: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 220
Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 221
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 223
Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 226
Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 227
Register 13: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 229
Register 14: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 231
Register 15: I²S MCLK Configuration (I2SMCLKCFG), offset 0x170 ..................................................... 232
January 23, 2012
19
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