LM3S5G51 Datasheet, PDF (911/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Stellaris^® LM3S5G51 Microcontroller
OTG A /
Host
OTG B /
Device
Register 11: USB Test Mode (USBTEST), offset 0x00F
USBTEST is an 8-bit register that is primarily used to put the USB controller into one of the four test
modes for operation described in the USB 2.0 Specification, in response to a SET FEATURE:
USBTESTMODE command. This register is not used in normal operation.
Note: Only one of these bits should be set at any time.
OTG A / Host Mode
USB Test Mode (USBTEST)
Base 0x4005.0000
Offset 0x00F
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
FORCEH FIFOACC FORCEFS
reserved
Type R/W R/W1S R/W
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
Bit/Field
7
6
5
Name
FORCEH
FIFOACC
FORCEFS
Type
R/W
R/W1S
R/W
Reset
0
0
0
Description
Force Host Mode
Value Description
1 Forces the USB controller to enter Host mode when the
SESSION bit is set, regardless of whether the USB controller is
connected to any peripheral. The state of the USB0DP and
USB0DM signals is ignored. The USB controller then remains in
Host mode until the SESSION bit is cleared, even if a Device is
disconnected. If the FORCEH bit remains set, the USB controller
re-enters Host mode the next time the SESSION bit is set.
0 No effect.
While in this mode, status of the bus connection may be read using the
DEV bit of the USBDEVCTL register. The operating speed is determined
from the FORCEFS bit.
FIFO Access
Value Description
1 Transfers the packet in the endpoint 0 transmit FIFO to the
endpoint 0 receive FIFO.
0 No effect.
This bit is cleared automatically.
Force Full-Speed Mode
Value Description
1 Forces the USB controller into Full-Speed mode upon receiving
a USB RESET.
0 The USB controller operates at Low Speed.
January 23, 2012
911
Texas Instruments-Production Data