LM3S5G51 Datasheet, PDF (658/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
3
2
1
0
Name
STP2
EPS
PEN
BRK
Type
R/W
R/W
R/W
R/W
Reset
0
Description
UART Two Stop Bits Select
Value Description
1 Two stop bits are transmitted at the end of a frame. The receive
logic does not check for two stop bits being received.
When in 7816 smartcard mode (the SMART bit is set in the
UARTCTL register), the number of stop bits is forced to 2.
0 One stop bit is transmitted at the end of a frame.
0
UART Even Parity Select
Value Description
1 Even parity generation and checking is performed during
transmission and reception, which checks for an even number
of 1s in data and parity bits.
0 Odd parity is performed, which checks for an odd number of 1s.
This bit has no effect when parity is disabled by the PEN bit.
0
UART Parity Enable
Value Description
1 Parity checking and generation is enabled.
0 Parity is disabled and no parity bit is added to the data frame.
0
UART Send Break
Value Description
1 A Low level is continually output on the UnTx signal, after
completing transmission of the current character. For the proper
execution of the break command, software must set this bit for
at least two frames (character periods).
0 Normal use.
658
January 23, 2012
Texas Instruments-Production Data