LM3S5G51 Datasheet, PDF (797/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Stellaris^® LM3S5G51 Microcontroller
Register 9: I²S Receive Module Configuration (I2SRXCFG), offset 0x808
This register controls the configuration of the receive module.
I2S Receive Module Configuration (I2SRXCFG)
Base 0x4005.4000
Offset 0x808
Type R/W, reset 0x1400.7DF0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
JST
DLY
SCP
LRP
reserved
RM
reserved
MSL
reserved
Type RO
RO
R/W
R/W
R/W
R/W
RO
R/W
RO
R/W
RO
RO
RO
RO
RO
RO
Reset
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSZ
SDSZ
reserved
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Reset
0
1
1
1
1
1
0
1
1
1
1
1
0
0
0
0
Bit/Field
31:30
29
Name
reserved
JST
Type
RO
R/W
Reset
0x0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Justification of Input Data
Value Description
0 The data is Left-Justified.
1 The data is Right-Justified.
28
DLY
R/W
1
Data Delay
Value Description
0 Data is latched on the next latching edge of I2S0RXSCK as
defined by the SCP bit. This bit should be clear in Left-Justified
or Right-Justified mode.
1 A one-I2S0RXSCK delay from the edge of I2S0RXWS is inserted
before data is latched. This bit should be set in I²S mode.
27
SCP
R/W
0
SCLK Polarity
Value Description
0 Data is latched on the rising edge and the I2S0RXWS signal
(when the MSL bit is set) is launched on the falling edge of
I2S0RXSCK.
1 Data is latched on the falling edge and the I2S0RXWS signal
(when the MSL bit is set) is launched on the rising edge of
I2S0RXSCK.
January 23, 2012
797
Texas Instruments-Production Data