LM3S5G51 Datasheet, PDF (23/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Stellaris^® LM3S5G51 Microcontroller
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 511
GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 513
GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 514
GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 515
GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 516
GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 517
GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 518
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 519
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 520
GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 521
GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 522
GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 523
GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 524
Watchdog Timers ......................................................................................................................... 525
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 529
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 530
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 531
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 533
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 534
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 535
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 536
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 537
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 538
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 539
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 540
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 541
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 542
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 543
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 544
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 545
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 546
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 547
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 548
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 549
Analog-to-Digital Converter (ADC) ............................................................................................. 550
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 573
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 574
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 576
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 578
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 581
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 583
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 588
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 589
Register 9: ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 591
Register 10: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 593
Register 11: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 595
Register 12: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 596
Register 13: ADC Control (ADCCTL), offset 0x038 ............................................................................. 598
January 23, 2012
23
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