LM3S5G51 Datasheet, PDF (85/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Stellaris^® LM3S5G51 Microcontroller
Table 2-4. Memory Map (continued)
Start
End
0x4005.A000
0x4005.B000
0x4005.C000
0x4005.D000
0x4005.E000
0x4005.F000
0x4006.0000
0x4006.1000
0x400F.C000
0x400F.D000
0x400F.E000
0x400F.F000
0x4010.0000
0x4200.0000
0x4400.0000
Private Peripheral Bus
0xE000.0000
0xE000.1000
0xE000.2000
0xE000.3000
0xE000.E000
0xE000.F000
0xE004.0000
0xE004.1000
0x4005.AFFF
0x4005.BFFF
0x4005.CFFF
0x4005.DFFF
0x4005.EFFF
0x4005.FFFF
0x4006.0FFF
0x400F.BFFF
0x400F.CFFF
0x400F.DFFF
0x400F.EFFF
0x400F.FFFF
0x41FF.FFFF
0x43FF.FFFF
0xDFFF.FFFF
0xE000.0FFF
0xE000.1FFF
0xE000.2FFF
0xE000.DFFF
0xE000.EFFF
0xE003.FFFF
0xE004.0FFF
0xFFFF.FFFF
Description
GPIO Port C (AHB aperture)
GPIO Port D (AHB aperture)
GPIO Port E (AHB aperture)
GPIO Port F (AHB aperture)
GPIO Port G (AHB aperture)
GPIO Port H (AHB aperture)
GPIO Port J (AHB aperture)
Reserved
Hibernation Module
Flash memory control
System control
µDMA
Reserved
Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
Reserved
For details,
see page ...
435
435
435
435
435
435
435
-
299
326
203
383
-
-
-
Instrumentation Trace Macrocell (ITM)
66
Data Watchpoint and Trace (DWT)
66
Flash Patch and Breakpoint (FPB)
66
Reserved
-
Cortex-M3 Peripherals (SysTick, NVIC, MPU and SCB)
115
Reserved
-
Trace Port Interface Unit (TPIU)
67
Reserved
-
2.4.1
Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region
has a defined memory type, and some regions have additional memory attributes. The memory
type and attributes determine the behavior of accesses to the region.
The memory types are:
■ Normal: The processor can re-order transactions for efficiency and perform speculative reads.
■ Device: The processor preserves transaction order relative to other transactions to Device or
Strongly Ordered memory.
■ Strongly Ordered: The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.
January 23, 2012
85
Texas Instruments-Production Data