LM3S5G51 Datasheet, PDF (22/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Table of Contents
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 417
DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 418
DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 419
DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 420
DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 421
General-Purpose Input/Outputs (GPIOs) ................................................................................... 422
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 436
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 437
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 438
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 439
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 440
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 441
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 442
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 443
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 445
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 446
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 448
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 449
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 450
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 451
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 452
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 454
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 456
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 457
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 459
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 460
Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 462
Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 464
Register 23: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 466
Register 24: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 467
Register 25: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 468
Register 26: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 469
Register 27: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 470
Register 28: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 471
Register 29: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 472
Register 30: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 473
Register 31: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 474
Register 32: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 475
Register 33: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 476
Register 34: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 477
General-Purpose Timers ............................................................................................................. 478
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 495
Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 496
Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 498
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 500
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 503
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 505
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 508
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January 23, 2012
Texas Instruments-Production Data