LM3S5G51 Datasheet, PDF (202/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

System Control
5.4 Register Map
Table 5-8 on page 202 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register's address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Additional Flash and ROM registers defined in the System Control register space are
described in the “Internal Memory” on page 316.
Table 5-8. System Control Register Map
Offset Name
Type
Reset
Description
0x000 DID0
0x004 DID1
0x008 DC0
0x010 DC1
0x014 DC2
0x018 DC3
0x01C DC4
0x020 DC5
0x024 DC6
0x028 DC7
0x02C DC8
0x030 PBORCTL
0x040 SRCR0
0x044 SRCR1
0x048 SRCR2
0x050 RIS
0x054 IMC
0x058 MISC
0x05C RESC
0x060 RCC
0x064 PLLCFG
0x06C GPIOHBCTL
0x070 RCC2
0x07C MOSCCTL
0x100 RCGC0
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
RO
R/W
R/W1C
R/W
R/W
RO
R/W
R/W
R/W
R/W
-
-
0x00FF.00BF
-
0x130F.5337
0xBFFF.8FFF
0x0004.F1FF
0x0F30.003F
0x0000.0013
0xFFFF.FFFF
0xFFFF.FFFF
0x0000.0002
0x00000000
0x00000000
0x00000000
0x0000.0000
0x0000.0000
0x0000.0000
-
0x078E.3AD1
-
0x0000.0000
0x07C0.6810
0x0000.0000
0x00000040
Device Identification 0
Device Identification 1
Device Capabilities 0
Device Capabilities 1
Device Capabilities 2
Device Capabilities 3
Device Capabilities 4
Device Capabilities 5
Device Capabilities 6
Device Capabilities 7
Device Capabilities 8 ADC Channels
Brown-Out Reset Control
Software Reset Control 0
Software Reset Control 1
Software Reset Control 2
Raw Interrupt Status
Interrupt Mask Control
Masked Interrupt Status and Clear
Reset Cause
Run-Mode Clock Configuration
XTAL to PLL Translation
GPIO High-Performance Bus Control
Run-Mode Clock Configuration 2
Main Oscillator Control
Run Mode Clock Gating Control Register 0
See
page
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January 23, 2012
Texas Instruments-Production Data