LM3S5G51 Datasheet, PDF (25/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Stellaris^® LM3S5G51 Microcontroller
Register 7:
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Register 28:
Register 29:
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 657
UART Control (UARTCTL), offset 0x030 ......................................................................... 659
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 663
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 665
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 669
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 673
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 677
UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 679
UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 680
UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 681
UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 682
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 683
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 684
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 685
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 686
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 687
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 688
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 689
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 690
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 691
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 692
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 693
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 694
Synchronous Serial Interface (SSI) ............................................................................................ 695
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 710
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 712
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 714
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 715
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 717
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 718
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 719
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 721
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 723
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 724
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 725
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 726
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 727
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 728
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 729
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 730
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 731
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 732
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 733
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 734
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 735
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 736
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 737
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 754
January 23, 2012
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