LM3S5G51 Datasheet, PDF (800/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Inter-Integrated Circuit Sound (I²S) Interface
Register 10: I²S Receive FIFO Limit (I2SRXLIMIT), offset 0x80C
This register sets the upper FIFO limit at which a FIFO service request is issued.
I2S Receive FIFO Limit (I2SRXLIMIT)
Base 0x4005.4000
Offset 0x80C
Type R/W, reset 0x0000.7FFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
LIMIT
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit/Field
31:16
15:5
4:0
Name
reserved
reserved
LIMIT
Type
RO
RO
R/W
Reset
0x0000
0x7FF
0x1F
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FIFO Limit
This field sets the FIFO level at which a FIFO service request is issued,
generating an interrupt or a µDMA transfer request.
The receive FIFO generates a service request when the number of items
in the FIFO is greater than the level specified by the LIMIT field. For
example, if the LIMIT field is set to 4, then a service request is
generated when there are more than 4 samples remaining in the transmit
FIFO.
800
January 23, 2012
Texas Instruments-Production Data