LM3S5G51 Datasheet, PDF (47/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Stellaris^® LM3S5G51 Microcontroller
1.3.1.3
1.3.1.4
1.3.1.5
1.3.2
1.3.2.1
Nested Vectored Interrupt Controller (NVIC) (see page 108)
The LM3S5G51 controller includes the ARM Nested Vectored Interrupt Controller (NVIC). The NVIC
and Cortex-M3 prioritize and handle all exceptions in Handler Mode. The processor state is
automatically stored to the stack on an exception and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The interrupt vector is fetched in parallel to the state
saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that
back-to-back interrupts can be performed without the overhead of state saving and restoration.
Software can set eight priority levels on 7 exceptions (system handlers) and 50 interrupts.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler
for safety critical applications
■ Dynamically reprioritizable interrupts
■ Exceptional interrupt handling via hardware implementation of required register manipulations
System Control Block (SCB) (see page 110)
The SCB provides system implementation information and system control, including configuration,
control, and reporting of system exceptions.
Memory Protection Unit (MPU) (see page 110)
The MPU supports the standard ARM7 Protected Memory System Architecture (PMSA) model. The
MPU provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
On-Chip Memory
The LM3S5G51 microcontroller is integrated with the following set of on-chip memory and features:
■ 64 KB single-cycle SRAM
■ 384 KB single-cycle Flash memory up to 50 MHz; a prefetch buffer improves performance above
50 MHz
■ Internal ROM loaded with StellarisWare software:
– Stellaris Peripheral Driver Library
– Stellaris Boot Loader
– Advanced Encryption Standard (AES) cryptography tables
– Cyclic Redundancy Check (CRC) error detection functionality
SRAM (see page 317)
The LM3S5G51 microcontroller provides 64 KB of single-cycle on-chip SRAM. The internal SRAM
of the Stellaris devices is located at offset 0x2000.0000 of the device memory map.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced
bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Data can be transferred to and from the SRAM using the Micro Direct Memory Access Controller
(µDMA).
January 23, 2012
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