LM3S5G51 Datasheet, PDF (485/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Stellaris^® LM3S5G51 Microcontroller
Timer B in the same module, and Timer B triggers Timer A in the next module. Care must be taken
that the TAWOT bit is never set in GPTM0. Figure 10-2 on page 485 shows how the GPTMCFG bit
affects the daisy chain. This function is valid for both one-shot and periodic modes.
Figure 10-2. Timer Daisy Chain
GP Timer N+1
10
GPTMCFG
Timer B
Timer A
Timer B ADC Trigger
Timer A ADC Trigger
GP Timer N
10
GPTMCFG
Timer B
Timer A
Timer B ADC Trigger
Timer A ADC Trigger
10.3.2.2
Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the Timer A and Timer B registers
are configured as an up-counter. When RTC mode is selected for the first time after reset, the
counter is loaded with a value of 0x1. All subsequent load values must be written to the GPTM
Timer A Interval Load (GPTMTAILR) register (see page 513). Table 10-7 on page 485 shows the
values that are loaded into the timer registers when the timer is enabled.
Table 10-7. Counter Values When the Timer is Enabled in RTC Mode
Register
TnR
TnV
Count Down Mode
Not available
Not available
Count Up Mode
0x1
0x1
The input clock on a CCP input is required to be 32.768 KHz in RTC mode. The clock signal is then
divided down to a 1-Hz rate and is passed along to the input of the counter.
When software writes the TAEN bit in the GPTMCTL register, the counter starts counting up from
its preloaded value of 0x1. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, the GPTM asserts the RTCRIS bit in GPTMRIS and continues counting
until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When the timer
value reaches the terminal count, the timer rolls over and continues counting up from 0x0. If the
RTC interrupt is enabled in GPTMIMR, the GPTM also sets the RTCMIS bit in GPTMMIS and
generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR.
In this mode, the GPTMTnR and GPTMTnV registers always have the same value.
In addition to generating interrupts, a μDMA trigger can be generated. The μDMA trigger is enabled
by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 366.
If the TASTALL bit in the GPTMCTL register is set, the timer does not freeze when the processor
is halted by the debugger if the RTCEN bit is set in GPTMCTL.
January 23, 2012
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