LM3S5G51 Datasheet, PDF (14/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Table of Contents
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 5-9.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Revision History .................................................................................................. 37
Documentation Conventions ................................................................................ 41
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 69
Processor Register Map ....................................................................................... 70
PSR Register Combinations ................................................................................. 75
Memory Map ....................................................................................................... 83
Memory Access Behavior ..................................................................................... 86
SRAM Memory Bit-Banding Regions .................................................................... 88
Peripheral Memory Bit-Banding Regions ............................................................... 88
Exception Types .................................................................................................. 94
Interrupts ............................................................................................................ 95
Exception Return Behavior ................................................................................. 100
Faults ............................................................................................................... 100
Fault Status and Fault Address Registers ............................................................ 102
Cortex-M3 Instruction Summary ......................................................................... 104
Core Peripheral Register Regions ....................................................................... 107
Memory Attributes Summary .............................................................................. 110
TEX, S, C, and B Bit Field Encoding ................................................................... 113
Cache Policy for Memory Attribute Encoding ....................................................... 114
AP Bit Field Encoding ........................................................................................ 114
Memory Region Attributes for Stellaris Microcontrollers ........................................ 114
Peripherals Register Map ................................................................................... 115
Interrupt Priority Levels ...................................................................................... 142
Example SIZE Field Values ................................................................................ 170
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 174
JTAG_SWD_SWO Signals (108BGA) ................................................................. 175
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 176
JTAG Instruction Register Commands ................................................................. 181
System Control & Clocks Signals (100LQFP) ...................................................... 185
System Control & Clocks Signals (108BGA) ........................................................ 185
Reset Sources ................................................................................................... 186
Clock Source Options ........................................................................................ 193
Possible System Clock Frequencies Using the SYSDIV Field ............................... 196
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 196
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 197
System Control Register Map ............................................................................. 202
RCC2 Fields that Override RCC Fields ............................................................... 223
Hibernate Signals (100LQFP) ............................................................................. 290
Hibernate Signals (108BGA) .............................................................................. 291
Hibernation Module Clock Operation ................................................................... 297
Hibernation Module Register Map ....................................................................... 299
Flash Memory Protection Policy Combinations .................................................... 320
User-Programmable Flash Memory Resident Registers ....................................... 324
Flash Register Map ............................................................................................ 324
μDMA Channel Assignments .............................................................................. 364
Request Type Support ....................................................................................... 366
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January 23, 2012
Texas Instruments-Production Data