LM3S5G51 Datasheet, PDF (1030/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Pulse Width Modulator (PWM)
Register 1: PWM Master Control (PWMCTL), offset 0x000
This register provides master control over the PWM generation blocks.
PWM Master Control (PWMCTL)
PWM0 base: 0x4002.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
GLOBALSYNC2 GLOBALSYNC1 GLOBALSYNC0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
1
0
Name
reserved
GLOBALSYNC2
GLOBALSYNC1
GLOBALSYNC0
Type
RO
R/W
R/W
R/W
Reset
0x0000
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Update PWM Generator 2
Value Description
1 Any queued update to a load or comparator register in PWM
generator 2 is applied the next time the corresponding counter
becomes zero.
0 No effect.
This bit automatically clears when the updates have completed; it cannot
be cleared by software.
Update PWM Generator 1
Value Description
1 Any queued update to a load or comparator register in PWM
generator 1 is applied the next time the corresponding counter
becomes zero.
0 No effect.
This bit automatically clears when the updates have completed; it cannot
be cleared by software.
Update PWM Generator 0
Value Description
1 Any queued update to a load or comparator register in PWM
generator 0 is applied the next time the corresponding counter
becomes zero.
0 No effect.
This bit automatically clears when the updates have completed; it cannot
be cleared by software.
1030
Texas Instruments-Production Data
January 23, 2012