LM3S5G51 Datasheet, PDF (950/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller

Universal Serial Bus (USB) Controller
Bit/Field
2
1
0
Name
UNDRN
FIFONE
TXRDY
Type
R/W
R/W
R/W
Reset
0
0
Description
Underrun
Value Description
0 No underrun.
1 An IN token has been received when TXRDY is not set.
Software must clear this bit.
FIFO Not Empty
Value Description
0 The FIFO is empty.
1 At least one packet is in the transmit FIFO.
0
Transmit Packet Ready
Value Description
0 No transmit packet is ready.
1 Software sets this bit after loading a data packet into the TX
FIFO.
This bit is cleared automatically when a data packet has been
transmitted. The EPn bit in the USBTXIS register is also set at this point.
TXRDY is also automatically cleared prior to loading a second packet
into a double-buffered FIFO.
950
January 23, 2012
Texas Instruments-Production Data