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LM3S5G51 Datasheet, PDF (1118/1266 Pages) Texas Instruments – Stellaris® LM3S5G51 Microcontroller
Signal Tables
Table 23-2. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Typea Description
PA4
I/O
TTL
GPIO port A bit 4.
CAN0Rx
I
TTL
CAN module 0 receive.
30
I2S0TXSCK
I/O
TTL
I2S module 0 transmit clock.
SSI0Rx
I
TTL
SSI module 0 receive.
PA5
I/O
TTL
GPIO port A bit 5.
CAN0Tx
O
TTL
CAN module 0 transmit.
31
I2S0TXWS
I/O
TTL
I2S module 0 transmit word select.
SSI0Tx
O
TTL
SSI module 0 transmit.
32
VDD
-
Power Positive supply for I/O and some logic.
33
GND
-
Power Ground reference for logic and I/O pins.
PA6
I/O
TTL
GPIO port A bit 6.
CAN0Rx
I
TTL
CAN module 0 receive.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
I2C1SCL
I/O
OD
I2C module 1 clock.
34
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
U1CTS
I
TTL
UART module 1 Clear To Send modem flow control input signal.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
PA7
I/O
TTL
GPIO port A bit 7.
CAN0Tx
O
TTL
CAN module 0 transmit.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
CCP4
I/O
TTL
Capture/Compare/PWM 4.
35
I2C1SDA
I/O
OD
I2C module 1 data.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
U1DCD
I
TTL
UART module 1 Data Carrier Detect modem status input signal.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
PG7
I/O
TTL
GPIO port G bit 7.
36
CCP5
I/O
TTL
Capture/Compare/PWM 5.
PhB1
I
TTL
QEI module 1 phase B.
PG6
I/O
TTL
GPIO port G bit 6.
Fault1
I
TTL
PWM Fault 1.
37
I2S0RXWS
I/O
TTL
I2S module 0 receive word select.
PhA1
I
TTL
QEI module 1 phase A.
U1RI
I
TTL
UART module 1 Ring Indicator modem status input signal.
VDDC
38
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 25-6 on page 1191.
1118
Texas Instruments-Production Data
January 23, 2012