C8051F850-C-GM Datasheet, PDF (98/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

In Burst Mode, tracking is determined by the settings in ADPWR and ADTK. Settling time requirements
may need adjustment in some applications. Refer to “14.2.4. Settling Time Requirements” on page 84 for
more details.
Notes:
Setting ADTM to 1 will insert an additional 4 SAR clocks of tracking before each conversion,
regardless of the settings of ADPWR and ADTK.
When using Burst Mode, care must be taken to issue a convert start signal no faster than once
every four SYSCLK periods. This includes external convert start signals. The ADC will ignore
convert start signals which arrive before a burst is finished.
System Clock
Convert Start
ADTM = 1
ADEN = 0
Powered
Down
P o w e r-U p
and Track
T
4
C
T
T
4
C
T
T
4
C
T
T
4
C
P o w e re d
Down
P o w e r-U p
and Track
T C..
ADTM = 0
ADEN = 0
Powered
Down
P o w e r-U p
and Track
ADPWR
C TC TC TC
ADTK
Powered
Down
P o w e r-U p
and Track
T C..
T = Tracking set by ADTK
T4 = Tracking set by ADTM (4 SAR clocks)
C = Converting
Figure 14.3. Burst Mode Tracking Example with Repeat Count Set to 4
14.2.4. Settling Time Requirements
A minimum amount of tracking time is required before each conversion can be performed, to allow the
sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0
sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note
that when ADTM is set to 1, four SAR clocks are used for tracking at the start of every conversion. Large
external source impedance will increase the required tracking time.
Figure 14.4 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 14.1. When measuring any internal source, R_TOTAL
reduces to R_MUX. See the electrical specification tables for ADC0 minimum settling time requirements as
well as the mux impedance and sampling capacitor values.
t
=
ln


S^-2---A^{-n-}
×
R_TOTALC_SAMPLE
Equation 14.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R_TOTAL is the sum of the AMUX0 resistance and any external source resistance.
84
Rev. 1.0