C8051F850-C-GM Datasheet, PDF (228/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

1. Enable the VDD supply monitor (VMONEN = 1).
2. Wait for the VDD supply monitor to stabilize (optional).
3. Enable the VDD monitor as a reset source in the RSTSRC register.
22.4. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state.
Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of
the RST pin may be necessary to avoid erroneous noise-induced resets. The PINRSF flag is set on exit
from an external reset.
22.5. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the MCD time window, the one-shot will time out and generate a
reset. After a MCD reset, the MCDRSF flag will read 1, signifying the MCD as the reset source; otherwise,
this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it.
The state of the RST pin is unaffected by this reset.
22.6. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag. Comparator0 should
be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the output
from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting input voltage
(on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset state. After a
Comparator0 reset, the C0RSEF flag will read 1 signifying Comparator0 as the reset source; otherwise,
this bit reads ‘0’. The state of the RST pin is unaffected by this reset.
22.7. Watchdog Timer Reset
The programmable Watchdog Timer (WDT) can be used to prevent software from running out of control
during a system malfunction. The WDT function can be enabled or disabled by software as described in
the watchdog timer section. If a system malfunction prevents user software from updating the WDT, a reset
is generated and the WDTRSF bit is set to ‘1’. The state of the RST pin is unaffected by this reset.
22.8. Flash Error Reset
If a flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
A flash write or erase is attempted above user code space.
A flash read is attempted above user code space.
A program read is attempted above user code space (i.e. a branch instruction to the reserved
area).
A flash read, write or erase attempt is restricted due to a flash security setting.
The FERROR bit is set following a flash error reset. The state of the RST pin is unaffected by this reset.
22.9. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit. The SWRSF bit will read 1 following a
software forced reset. The state of the RST pin is unaffected by this reset.
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