C8051F850-C-GM Datasheet, PDF (10/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

Table 1.2. Power Consumption (Continued)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Digital Core Supply Current (–Ix Devices, -40°C to +125°C)
Normal Mode—Full speed
I_DD
with code executing from flash
Idle Mode—Core halted with
I_DD
peripherals running
F_SYSCLK = 24.5 MHz²
F_SYSCLK = 1.53 MHz²
F_SYSCLK = 80 kHz³, T_A = 25 °C
F_SYSCLK = 80 kHz³
F_SYSCLK = 24.5 MHz²
F_SYSCLK = 1.53 MHz²
F_SYSCLK = 80 kHz³, T_A = 25 °C
F_SYSCLK = 80 kHz³
Stop Mode—Core halted and
I_DD
all clocks stopped, Supply
monitor off.
Internal LDO ON, T_A = 25 °C
Internal LDO ON
Internal LDO OFF
— 4.45 5.25 mA
— 915 1600 μA
— 250 290 μA
— 250 725 μA
— 2.05 2.6 mA
— 550 1000 μA
— 125 130 μA
— 125 550 μA
— 105 120 μA
— 105 270 μA
— 0.2
—
μA
Analog Peripheral Supply Currents (Both –Gx and –Ix Devices)
High-Frequency Oscillator
I_HFOSC
Operating at 24.5 MHz,
T_A = 25 °C
— 155 —
µA
Low-Frequency Oscillator
ADC0 Always-on⁴
I_LFOSC
I_ADC
Operating at 80 kHz,
T_A = 25 °C
800 ksps, 10-bit conversions or
200 ksps, 12-bit conversions
Normal bias settings
V_DD = 3.0 V
— 3.5
—
µA
— 845 1200 µA
250 ksps, 10-bit conversions or
62.5 ksps 12-bit conversions
Low power bias settings
V_DD = 3.0 V
— 425 580 µA
ADC0 Burst Mode, 10-bit sin- I_ADC
gle conversions, external ref-
erence
200 ksps, V_DD = 3.0 V
100 ksps, V_DD = 3.0 V
10 ksps, V_DD = 3.0 V
— 370 —
µA
— 185 —
µA
—
19
—
µA
Notes:
1. Currents are additive. For example, where I_DD is specified and the mode is not mutually exclusive, enabling the
functions increases supply current by the specified amount.
2. Includes supply current from internal regulator, supply monitor, and High Frequency Oscillator.
3. Includes supply current from internal regulator, supply monitor, and Low Frequency Oscillator.
4. ADC0 always-on power excludes internal reference supply current.
5. The internal reference is enabled as-needed when operating the ADC in burst mode to save power.
9
Rev. 1.0