C8051F850-C-GM Datasheet, PDF (172/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

20.4. PWM Waveform Generation
The PCA can generate edge- or center-aligned PWM waveforms with resolutions of 8, 9, 10, 11 or 16 bits.
PWM resolution depends on the module setup, as specified within the individual module PCA0CPMn
registers as well as the PCA0PWM register. Modules can be configured for 8-11 bit mode, or for 16-bit
mode individually using the PCA0CPMn registers. All modules configured for 8-11 bit mode will have the
same resolution, specified by the PCA0PWM register. When operating in one of the PWM modes, each
module may be individually configured for center or edge-aligned PWM waveforms. Each channel has a
single bit in the PCA0CENT register to select between the two options.
20.4.1. Edge Aligned PWM
When configured for edge-aligned mode, a module will generate an edge transition at two points for every
2^N PCA clock cycles, where N is the selected PWM resolution in bits. In edge-aligned mode, these two
edges are referred to as the “match” and “overflow” edges. The polarity at the output pin is selectable, and
can be inverted by setting the appropriate channel bit to ‘1’ in the PCA0POL register. Prior to inversion, a
match edge sets the channel to logic high, and an overflow edge clears the channel to logic low.
The match edge occurs when the the lowest N bits of the module’s PCA0CPn register match the
corresponding bits of the main PCA0 counter register. For example, with 10-bit PWM, the match edge will
occur any time bits 9-0 of the PCA0CPn register match bits 9-0 of the PCA0 counter value.
The overflow edge occurs when an overflow of the PCA0 counter happens at the desired resolution. For
example, with 10-bit PWM, the overflow edge will occur when bits 0-9 of the PCA0 counter transition from
all 1’s to all 0’s. All modules configured for edge-aligned mode at the same resolution will align on the
overflow edge of the waveforms.
An example of the PWM timing in edge-aligned mode for two channels is shown in Figure 20.6. In this
example, the CEX0POL and CEX1POL bits are cleared to 0.
PCA Clock
Counter (PCA0) ^{0xFFFF 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005}
Capture / Compare
(PCA0CP0)
0x0001
Output (CEX0)
match edge
Capture / Compare
(PCA0CP1)
0x0005
Output (CEX1)
overflow edge
match edge
Figure 20.6. Edge-Aligned PWM Timing
For a given PCA resolution, the unused high bits in the PCA0 counter and the PCA0CPn compare
registers are ignored, and only the used bits of the PCA0CPn register determine the duty cycle.
Equation 20.2 describes the duty cycle when CEXnPOL in the PCA0POL regsiter is cleared to 0.
Equation 20.3 describes the duty cycle when CEXnPOL in the PCA0POL regsiter is set to 1. A 0% duty
cycle for the channel (with CEXnPOL = 0) is achieved by clearing the module’s ECOM bit to 0. This will
152
Rev. 1.0