C8051F850-C-GM Datasheet, PDF (89/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

13. Power Management and Internal Regulator
All internal circuitry on the C8051F85x/86x devices draws power from the VDD supply pin. Circuits with
external connections (I/O pins, analog muxes) are powered directly from the VDD supply voltage, while
most of the internal circuitry is supplied by an on-chip LDO regulator. The regulator output is fully internal to
the device, and is available also as an ADC input or reference source for the comparators and ADC.
The devices support the standard 8051 power modes: idle and stop. For further power savings in stop
mode, the internal LDO regulator may be disabled, shutting down the majority of the power nets on the
device.
Although the C8051F85x/86x has idle and stop modes available, more control over the device power can
be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be
disabled when not in use and placed in low power mode. Digital peripherals, such as timers and serial
buses, have their clocks gated off and draw little power when they are not in use.
13.1. Power Modes
Idle mode halts the CPU while leaving the peripherals and clocks active. In stop mode, the CPU is halted,
all interrupts and timers are inactive, and the internal oscillator is stopped (analog peripherals remain in
their selected states; the external oscillator is not affected). Since clocks are running in Idle mode, power
consumption is dependent upon the system clock frequency and the number of peripherals left in active
mode before entering Idle. Stop mode consumes the least power because the majority of the device is shut
down with no clocks active. The Power Control Register (PCON) is used to control the C8051F85x/86x's
Stop and Idle power management modes.
13.1.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter idle mode as
soon as the instruction that sets the bit completes execution. All internal registers and memory maintain
their original data. All analog and digital peripherals can remain active during idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during the
execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode when a future
interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an instruction that has two
or more opcode bytes, for example:
// in ‘C’:
PCON |= 0x01;
// set IDLE bit
PCON = PCON;
// ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h
MOV PCON, PCON
; set IDLE bit
; ... followed by a 3-cycle dummy instruction
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby
terminate the idle mode. This feature protects the system from an unintended permanent shutdown in the
event of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be
disabled by software prior to entering the Idle mode if the WDT was initially configured to allow this
operation. This provides the opportunity for additional power savings, allowing the system to remain in the
Idle mode indefinitely, waiting for an external stimulus to wake up the system.
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