C8051F850-C-GM Datasheet, PDF (30/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

2.5. Communications and other Digital Peripherals
2.5.1. Universal Asynchronous Receiver/Transmitter (UART0)
The UART uses two signals (TX and RX) and a predetermined fixed baud rate to provide asynchronous
communications with other devices.
The UART module provides the following features:
Asynchronous transmissions and receptions.
Baud rates up to SYSCLK / 2 (transmit) or SYSCLK / 8 (receive).
8- or 9-bit data.
Automatic start and stop generation.
2.5.2. Serial Peripheral Interface (SPI0)
SPI is a 3- or 4-wire communication interface that includes a clock, input data, output data, and an optional
select signal.
The SPI module includes the following features:
Supports 3- or 4-wire master or slave modes.
Supports external clock frequencies up to SYSCLK / 2 in master mode and SYSCLK / 10 in slave
mode.
Support for all clock phase and polarity modes.
8-bit programmable clock rate.
Support for multiple masters on the same data lines.
2.5.3. System Management Bus / I2C (SMBus0)
The SMBus interface is a two-wire, bi-directional serial bus compatible with both I2C and SMBus protocols.
The two clock and data signals operate in open-drain mode with external pull-ups to support automatic bus
arbitration.
Reads and writes to the interface are byte-oriented with the SMBus interface autonomously controlling the
serial transfer of the data. Data can be transferred at up to 1/8th of the system clock as a master or slave,
which can be faster than allowed by the SMBus / I2C specification, depending on the clock source used. A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple
masters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and
synchronization, arbitration logic, and start/stop control and generation.
The SMBus module includes the following features:
Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds.
Support for master, slave, and multi-master modes.
Hardware synchronization and arbitration for multi-master mode.
Clock low extending (clock stretching) to interface with faster masters.
Hardware support for 7-bit slave and general call address recognition.
Firmware support for 10-bit slave address decoding.
Ability to inhibit all slave states.
Programmable data setup/hold times.
2.5.4. 16/32-bit CRC (CRC0)
The CRC module is designed to provide hardware calculations for flash memory verification and
communications protocols. The CRC module supports the standard CCITT-16 16-bit polynomial (0x1021),
and includes the following features:
Support for four CCITT-16 polynomial.
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