C8051F850-C-GM Datasheet, PDF (263/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

Table 24.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) (Continued)
Values Read
Values to
Write
Current SMbus State
Typical Response Options
Set ACK for next data byte;
Read SMB0DAT.
0 0 1 1000
Set NACK to indicate next data
byte as the last data byte;
0
0
1
A master data byte was received; ACK
sent.
Read SMB0DAT.
Initiate repeated START.
0 0 0 1000
1 0 0 1110
1000
Switch to Master Transmitter
0 0 X 1100
Mode (write to SMB0DAT before
clearing SI).
Read SMB0DAT; send STOP. 0 1 0 —
0
0
0
A master data byte was received;
NACK sent (last byte).
Read SMB0DAT; Send STOP
followed by START.
Initiate repeated START.
1 1 0 1110
1 0 0 1110
Switch to Master Transmitter
0 0 X 1100
Mode (write to SMB0DAT before
clearing SI).
0
0
0
A slave byte was transmitted; NACK
received.
No action required (expecting
STOP condition).
0 0 X 0001
0100
0
0
1
A slave byte was transmitted; ACK
received.
Load SMB0DAT with next data _{0 0 X 0100}
byte to transmit.
0
1
X
A Slave byte was transmitted; error
detected.
No action required (expecting
Master to end transfer).
0 0 X 0001
An illegal STOP or bus error was
0101 0 X X detected while a Slave Transmission Clear STO.
was in progress.
00X —
Rev. 1.0
238