C8051F850-C-GM Datasheet, PDF (243/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

Register 23.2. SPI0CN: SPI0 Control
Bit
7
6
5
4
3
2
1
0
Name
SPIF
WCOL
MODF RXOVRN
NSSMD
TXBMT SPIEN
Type
RW
RW
RW
RW
RW
R
RW
Reset
0
0
0
0
0
1
1
0
SFR Address: 0xF8 (bit-addressable)
Table 23.3. SPI0CN Register Bit Descriptions
Bit
Name
Function
7
SPIF SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts are
enabled, an interrupt will be generated. This bit is not automatically cleared by hardware,
and must be cleared by software.
6
WCOL Write Collision Flag.
This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When this
occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written. If
SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically
cleared by hardware, and must be cleared by software.
5
MODF Mode Fault Flag.
This bit is set to logic 1 by hardware when a master mode collision is detected (NSS is
low, MSTEN = 1, and NSSMD = 01). If SPI interrupts are enabled, an interrupt will be
generated. This bit is not automatically cleared by hardware, and must be cleared by
software.
4
RXOVRN Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware when the receive buffer still holds unread data from
a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift reg-
ister. If SPI interrupts are enabled, an interrupt will be generated. This bit is not automat-
ically cleared by hardware, and must be cleared by software.
3:2
NSSMD Slave Select Mode.
Selects between the following NSS operation modes:
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
10: 4-Wire Single-Master Mode. NSS is an output and logic low.
11: 4-Wire Single-Master Mode. NSS is an output and logic high.
1
TXBMT Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer. When
data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic
1, indicating that it is safe to write a new byte to the transmit buffer.
Rev. 1.0
220